1. Field of the Invention
The present invention is directed to testing application specific integrated circuit (ASIC) designs. More specifically, but without limitation thereto, the present invention is directed to an on-chip scan clock generator for generating multiple scan clock signals during testing of an ASIC design.
2. Description of the Prior Art
In testing application specific integrated circuit (ASIC) designs, complex clock structures used for the operating or functional mode of the ASIC must be simplified for scan test mode, for example, by multiplexing the functional mode clock signals with the scan clock signal so that the clock inputs of all flip flops in the ASIC may be accessed from the available input pins of the ASIC. The term “flip flop” is used herein to include all types of devices in an integrated circuit that have a clocked input, including but not limited to memory circuits. The scan clock signal may differ substantially from the functional mode clock signals at each flip flop, resulting in possible timing violations in the scan test mode which would not occur in the functional mode. These timing violations may be overlooked due to a lack of understanding of the differences between functional mode clocking versus scan clocking.
Previous approaches for avoiding some of the timing problems include arbitrary capture scan clocking at the cost of higher scan vector counts and either a corresponding increase in tester time or a lower fault coverage.